The present invention concerns a semiconductor device with data input buffers, and more particularly means for reducing skew of a clock signal to the data input buffers.
As the semiconductor memory device is developed to carry out synchronous operation at higher speed, the setup/hold time has become more important factors to properly control the device. However, the conventional circuit technology does not satisfactorily meet the requirements for the setup/hold time and control. FIG. 1 illustrates a conventional semiconductor device, which includes five input/output pads 10, 12, 14, 16 and 18, corresponding data output buffers 20, 22, 24, 26 and 28, and corresponding data input buffers 30,32,34,36 and 38. As shown in FIG. 1, the input and output buffers 20 to 28 and 30 to 38 are arranged with the same intervals as the data input/output pads 10 to 18. In this case, the skewing of the clock/control signals CLK/CTL to the data input buffers increase proportionately along the length of the transfer lines 40 and 42 going from the first data input buffer 30 corresponding to the first input/output pad 10 to the last data input buffer 38 corresponding to the fifth input/output pad 18 along the transfer lines 40 and 42, so that the margin of the setup/hold time is reduced to make it hard to control the buffers.
It is an object of the present invention to provide a semiconductor device with means to improve margin of the setup/hold time.
According to an embodiment of the present invention, a semiconductor device comprises a plurality of input/output pads, and a plurality of input buffers for receiving external signals synchronized with a clock signal through corresponding ones of the input/output pads, wherein the input buffers are arranged adjacent to each other to minimize skewing of the clock signal to the input buffers.
The present invention will now described more specifically with reference to the drawings attached only by way of examples.